FCN R50
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FCN R50
Semantic segmentation, 21 classes, 520 × 520 RGB, native eval with auxiliary output. Shapes exclude batch.
LibreYOLO
FCN R50
Semantic segmentation, 21 classes, 520 × 520 RGB, native eval with auxiliary output. Shapes exclude batch.
Dilated ResNet backbone
Input RGB
3 × 520 × 520
ImageNet normalization
(x-mean)/std, per RGB channel
Conv2d 7×7, stride 2
3 to 64; padding 3
BatchNorm2d + ReLU
64 × 260 × 260
MaxPool2d 3×3, stride 2
64 × 130 × 130; padding 1
Bottleneck stage 1, n=3
256 × 130 × 130; width 64
Bottleneck stage 2, n=4
512 × 65 × 65; width 128
Bottleneck stage 3, n=6
1024 × 65 × 65; width 256
Bottleneck stage 4, n=3
2048 × 65 × 65; width 512
Output stride 8. Stage 3/4 replace spatial strides with dilation.
S3
S4
FCN heads
From stage 4 (S4)
2048 × 65 × 65
Conv2d 3×3
2048 to 512; s=1, p=1, bias=False
BatchNorm2d
512 channels
ReLU
Dropout 0.1
Identity in eval
Conv2d 1×1
512 to 21; bias=True
Bilinear resize to 520 × 520
align_corners=False
main logits
21 × 520 × 520
From stage 3 (S3)
1024 × 65 × 65
Conv2d 3×3
1024 to 256; s=1, p=1, bias=False
BatchNorm2d
256 channels
ReLU
Dropout 0.1
Identity in eval
Conv2d 1×1
256 to 21; bias=True
Bilinear resize to 520 × 520
align_corners=False
aux logits
21 × 520 × 520
Native output is an OrderedDict with out and aux; both paths execute during eval.
The public semantic result can use argmax over the 21 out channels.
This is the dilated-ResNet adaptation, not the original VGG FCN-8s topology.
Stage 1 bottlenecks (n=3)
First block
Input
64 channels
Conv2d 1×1
64 to 64, stride 1
BatchNorm2d
64 channels
ReLU
Conv2d 3×3
64 to 64; s=1, d=p=1
BatchNorm2d
64 channels
ReLU
Conv2d 1×1
64 to 256, stride 1
BatchNorm2d
256 channels
+
Conv 1×1
64 to 256; s=1
BatchNorm
256 channels
ReLU
Conv bias=False; addition precedes final ReLU.
Repeated block, n=2
Input
256 channels
Conv2d 1×1
256 to 64, stride 1
BatchNorm2d
64 channels
ReLU
Conv2d 3×3
64 to 64; s=1, d=p=1
BatchNorm2d
64 channels
ReLU
Conv2d 1×1
64 to 256, stride 1
BatchNorm2d
256 channels
+
ReLU
Conv bias=False; addition precedes final ReLU.
s: stride; d: dilation; p: padding. First block projects the residual branch.
Stage 2 bottlenecks (n=4)
First block
Input
256 channels
Conv2d 1×1
256 to 128, stride 1
BatchNorm2d
128 channels
ReLU
Conv2d 3×3
128 to 128; s=2, d=p=1
BatchNorm2d
128 channels
ReLU
Conv2d 1×1
128 to 512, stride 1
BatchNorm2d
512 channels
+
Conv 1×1
256 to 512; s=2
BatchNorm
512 channels
ReLU
Conv bias=False; addition precedes final ReLU.
Repeated block, n=3
Input
512 channels
Conv2d 1×1
512 to 128, stride 1
BatchNorm2d
128 channels
ReLU
Conv2d 3×3
128 to 128; s=1, d=p=1
BatchNorm2d
128 channels
ReLU
Conv2d 1×1
128 to 512, stride 1
BatchNorm2d
512 channels
+
ReLU
Conv bias=False; addition precedes final ReLU.
s: stride; d: dilation; p: padding. First block projects the residual branch.
Stage 3 bottlenecks (n=6)
First block
Input
512 channels
Conv2d 1×1
512 to 256, stride 1
BatchNorm2d
256 channels
ReLU
Conv2d 3×3
256 to 256; s=1, d=p=1
BatchNorm2d
256 channels
ReLU
Conv2d 1×1
256 to 1024, stride 1
BatchNorm2d
1024 channels
+
Conv 1×1
512 to 1024; s=1
BatchNorm
1024 channels
ReLU
Conv bias=False; addition precedes final ReLU.
Repeated block, n=5
Input
1024 channels
Conv2d 1×1
1024 to 256, stride 1
BatchNorm2d
256 channels
ReLU
Conv2d 3×3
256 to 256; s=1, d=p=2
BatchNorm2d
256 channels
ReLU
Conv2d 1×1
256 to 1024, stride 1
BatchNorm2d
1024 channels
+
ReLU
Conv bias=False; addition precedes final ReLU.
s: stride; d: dilation; p: padding. First block projects the residual branch.
Stage 4 bottlenecks (n=3)
First block
Input
1024 channels
Conv2d 1×1
1024 to 512, stride 1
BatchNorm2d
512 channels
ReLU
Conv2d 3×3
512 to 512; s=1, d=p=2
BatchNorm2d
512 channels
ReLU
Conv2d 1×1
512 to 2048, stride 1
BatchNorm2d
2048 channels
+
Conv 1×1
1024 to 2048; s=1
BatchNorm
2048 channels
ReLU
Conv bias=False; addition precedes final ReLU.
Repeated block, n=2
Input
2048 channels
Conv2d 1×1
2048 to 512, stride 1
BatchNorm2d
512 channels
ReLU
Conv2d 3×3
512 to 512; s=1, d=p=4
BatchNorm2d
512 channels
ReLU
Conv2d 1×1
512 to 2048, stride 1
BatchNorm2d
2048 channels
+
ReLU
Conv bias=False; addition precedes final ReLU.
s: stride; d: dilation; p: padding. First block projects the residual branch.
Shared family variable N3: 6 for r50, 23 for r101. All other stage counts and dimensions are identical.
ResNet backbone comes from torchvision (BSD-3-Clause); native FCN head and orchestration are in LibreYOLO.
Source: libreyolo/models/fcn/nn.py and model.py. Revision a4d0ecc9e17f.
libreyolo.com